Techniques to extract MOS CAP parameters from C-V measurement.

Introduction: 

From the C-V measurement, we are able to extract the oxide thickness, flat and voltage, threshold voltage, effective oxide charges, and substrate doping concentration. The detailed techniques are discussed below:

Oxide thickness: 

From the measured C-V, and relation as shown in equation (1), we can estimate the oxide thickness is measured in the MOS structure. The Cox-accum is the strong accumulation capacitance value that is measured.

Figure 1: C-V curve 

Equation (1)

Flat capacitance and voltage:

In my previous discussion, I have clearly mentioned band bending and flat band, depletion conditions. It is difficult to get a flat band because all the surfaces have defects that are dangling bonds that create band bending so it is necessary the amount of bending in terms of voltage is effective for device operation considerations. Flat band condition in C-V measurement can be obtained. The gate voltage required to get a flat band is called flat band voltage(V_FB). The surface potential is zero in this condition because the band is flat. This voltage and its shift are widely used to judge device parameters, especially oxide charges. We can estimate flat band voltage through the C-V measurement of MOS CAP. First, flat band capacitance is calculated by oxide-capacitance and Debye length One important point is that the flat band capacitance is invalid if the interface trap is too large (over 10¹²). The C_ox means the value of the capacitance at a strong accumulation point. The Debye length is an indicator of the distance to which an electrical interaction can be sensed in the semiconductor. Once we know the flat band capacitance then from the position of the flat band capacitance, we can estimate the corresponding flat band voltage. By using equations (2) and (3) we can get the required information to estimate the flat band capacitance.

Equation (2)

Equation (3)

Effective oxide charge density:

The effective oxide charge (Qi) is a combination of fixed charge, oxide trapped charge, and mobile ionic charge. In C-V measurement, we cannot distinguish them. Temperature cycling can be a way to distinguish them. We only assume the charge is in between the semiconductor-oxide interface. Now, to estimate the flat effective oxide charge density simply calculate the difference of metal-semiconductor work function difference, and using equation (4) we have the relation of effective oxide charge. If we simply divide the charge by the electron’s charge (q) then we get the effective oxide-charge density. 

Equation (4)

Substrate doping concentration: Please check an example of it here. Please also find a detailed discussion about Magnetic phase transition, structural analysis, and crystallography understanding in the link.

Judge your MOS CAP C-V measurement conditions.

Introduction 

It is very important to judge mainly volatile or non-volatile metal-oxide-semiconductor field effect transistor (MOSFET) devices for the computer system. The purpose of MOSFET is to switch or retain memory information permanently. The C-V measurement is one of the strong techniques to judge the device’s quality. This is also useful to evaluate new materials as well. We can know useful information about doping density in the semiconductor, carrier lifetimes, oxide thickness, oxide charges, interface trap density, mobile ions, etc. Therefore, understanding the detail of C-V measurement is of prime interest.

Fundamentals of MOS capacitor

For the measurement, it is necessary to the fabricated device in the structure of the Metal/Oxide/Semiconductor/Metal structure. This is like a MOS capacitor as shown in figure 1. In the structure, the semiconductor and bottom metal electrode acts as cathode plate. The top metal on the insulator acts as another electrode (anode). This is complete like a typical capacitor structure. We simply determine the capacitance from C = A (K/d), where A is the area of the capacitor top electrode, K is the dielectric constant of the insulator, and d is the separation distance between the two electrodes. It is clearly seen from the relation that the larger the A and K, and the thinner the d then the higher the capacitance. Anyway, the semiconductor capacitance values range from nano-farads to pico-farads or smaller. C-V measurement concepts: Two ways we can measure the C-V. 1. Quasistatic 2. High frequency. 

Figure 1: Cross-sectional MOS cap structure and measurement configuration

Quasistatic condition 

This is corresponded to close equilibrium. By convention, the quasistatic C-V measurement is made by the sweeping bias voltage applied to the MOS capacitor resulting in the semiconductor surface changes from inversion to depletion and then to accumulation. In this process, the displacement current is measured as a function of time. The displacement current is the transient charging current of the MOS capacitor. Actually, there is no real current flowing through the oxide layer. This quasistatic measurement is useful when the oxide material is not leaky. If it is leaky conduction current will be added to the displacement current and measurements will be inaccurate. For high-quality oxide material, the leaky current is negligible. However, the good point is that modern computer-driven C-V measurement can correct the leakage current. Surely, the integration of charging current results in the measurement of the stored charge in the MOS capacitor. i.e., CV=Q. It is clear that, if the surface of the semiconductor is either in accumulation or inversion denotes the charged mobile carriers are just beneath the oxide. Finally, the maximum capacitance measured is nothing but the capacitance of the oxide layer alone Then, C_max= C_oxA, and A is the area of the gate electrode contact. On the other hand, if the semiconductor is depleted then there is no layer of mobile carriers underneath the oxide/semiconductor interface. The mobile carriers are present underneath the depletion region. Then, in the depletion, the measured C is consisting of the series combination of oxide and capacitance of the depletion region. This series combination means less than C_max. In the measurement, the voltage is swept from inversion to accumulation then capacitance decreases C_max towards minimum. Equation 1 shows the expected C_min relation.

The detailed behaviors are shown in figure 2. Here, x_o and K are the thickness and dielectric constant of the oxide material. X_d and K­_s are the maximum thickness and dielectric constant of the depletion layer (semiconductor part). A note to keep in mind is that there is an electrical charge are still existed within the depletion region due to doping of the semiconductor i.e ionized impurity atoms. The good point is that these ionized charges do not affect or contribute to the displacement current due to its static nature. But at a high temperature, they may move so care about temperature is essential. Usually, room temperature measurement does not affect them. 

Figure 2: Quasistatic C-V response ( p-type semiconductor) 

Earlier we discussed quasistatic measurements where the capacitance is directly measured by the integration of charging current. It requires the application of bias voltages across the capacitor with a superimposed AC signal (Figure 1). Typically, AC frequencies from 10 kHz to 10 MHz are considered for these measurements. The DC bias functions as sweep voltage that drive the capacitor from the accumulation region to the depletion region and goes into inversion as shown in figure 2 or the reverse way. Depending on the polarity of the DC bias and carrier type in the semiconductor the accumulation and depletion occur. The accumulated majority carrier near the surface of the semiconductor cannot pass through the insulator which results in a capacitance maximum in the accumulation region as shown in figure 3. 

Figure 3: High-frequency C-V (p-type semiconductor)

In this case, the capacitance measured under conditions of accumulation and depletion can be expected to be the same as observed in quasistatic measurements. If the frequency of the AC signal is high enough, then the capacitance measured under a condition of inversion is not the same as in the quasistatic case. The reason is the non-equilibrium behavior of the inversion layer. In the physical sense, the inversion layer should be formed from the minority carriers generated in the depletion region and swept to the surface by the electric field. From the bulk minority carriers also can diffuse. In simple understanding, the equilibrium conditions indicate that there is enough time for the inversion layer carrier concentration to respond to any changes in the applied field. In reality, if the semiconductor is good then the carrier generation -recombination processes occur slowly usually for silicon it is in the millisecond orders. So, if the applied AC voltage is in the MHz range, then the inversion layer responses very slowly to flow the signal and is similar to ionized dopant impurity atoms’ behaviors. Apparently, the inversion layer is fixed with the AC component. This behavior is shown in figure 3. The capacitance in the inversion layer is the series combination of oxide and depletion layer capacitance (fully depletion condition).

Deep depletion in C-V Measurements

We can measure capacitance versus voltage either by sweeping the applied voltage from accumulation to inversion (+ to - voltage for n-type; - to + for p-type) or inversion to accumulation. In the case of quasistatic measurements, the direction of the sweep makes essentially no difference in the C-V plot, because the MOS capacitor remains nearly at equilibrium. However, at high frequency, the C-V plot may differ in the inversion region depending on the direction and rate of the voltage sweep. This is due to the kinetics of the minority carrier generation as discussed earlier. If generation and recombination it takes a longer time (excellent substrate), then the inversion layer may not fully form during the fast switching from accumulation to inversion. This may increase the depletion layer than we expect for equilibrium conditions. We call this a deep depletion as mentioned in figure 4. 

Figure 4: Deep depletion sweep from accumulation to inversion

Such deep depletion should be avoided in conventional C-V measurement. Of course, we can take advantage of this situation to determine the time constant of carrier generation-recombination processes i.e minority carriers’ lifetime of the substrate. Anyway, at high frequency, we can find the onset of equilibrium behavior, i.e., MOS capacitance increases in inversion. The minority carrier lifetime can be estimated by determining the dependence of inversion capacitance on sweep rate. The derivative of this function extrapolated back to equilibrium conditions is the minority carrier lifetime. 

Practically high-frequency C-V measurements are nearly always made by sweeping the applied bias voltage from inversion to accumulation to eliminate deep depletion. A point to be noted is that by proper biasing and illumination of the surface the substrate surface is fully inverted for inversion layer formation by illumination. Of course, the sweep should be done without illumination. Of course, the voltage sweep itself should be made without illumination. The ideal MOS capacitance per unit area, C, follows equation 1. Finally, if the substrate doping is constant, an increase in oxide thickness reduces the capacitance of the oxide layer resulting in a reduction of MOS capacitance. Furthermore, the position of the depletion region as a function of bias moves to higher values of voltage magnitude so a higher voltage magnitude must be applied across a thicker oxide to obtain the same electric field magnitude at the oxide/semiconductor interface. Also, if oxide thickness is fixed but substrate doping causes a corresponding change in the depletion layer capacitance. This is well understood that increasing (or decreasing) substrate doping causes the maximum width of the depletion layer to be reduced (or increased). So, at fixed oxide thickness, the Cox remains fixed, but the Cmin varies with substrate doping. Please find information to be extracted from the C-V measurement. You may also have an interest in band bending and p-n junction detail. Please check also them.  

What are crystal structures? How to determine crystal structure by x-ray diffraction?

Introduction:

Crystal is a periodic representation of atoms in 3D lattice space. There are seven crystal systems. They are cubic, tetragonal, hexagonal, rhombohedral, orthorhombic, monoclinic, and triclinic. Very often students and researchers get into trouble at the beginning of their research to determine crystal structures. They can not judge their findings properly. One of the tools to investigate the crystal of a crystal specimen is XRD.

2theta-Omega scanning:

When we carry out the XRD 2theta-Omega to study the epitaxial growth. After the measurement, we can easily relate the angle theta with the lattice spacing along the c-axis. Hence from the measured data, with the help of the lattice relation with the d-value, we can find the information about the lattice parameters and hence about the corresponding crystal structure. The detail of the lattice relation of the seven-crystal is shown in figure 1. 

Figure 1: Seven crystal system and their lattice relation

However, only 2theta-omega scanning can not give information about the detail of the crystal system. Figure 2 shows peaks from the planes parallel to the c-axis of the substrate. From this measurement, we can also calculate the lattice mismatch of the crystal system. Please check our primitive discussion.

Figure2. 2theta-omega scanning by symmetric x-ray diffraction technique

Along with the measurement, there is phi-scanning which gives information about the symmetry of the crystal. The symmetry in this case is mainly we call rotational symmetry.  Figure 3 shows the rotational symmetry of MnAs/InAs/GaAs epitaxial growth. Here, hexagonal MnAs (six-fold) with 3-fold rotational symmetry of InAs and GaAs. 

Figure 3: Phi-scanning to see the symmetry of the MnAs/InAs/GaAs hetero-structure.

Besides, we also carry out omega or theta scanning only to judge the displacement of the c-axis of the epitaxial film from the c-axis of the substrate. This gives information about the tilting of the grown film. Figure 4 shows omega scanning which reveals the relation between substrate and film distribution on the substrate along the c-axis. Tilting is usually visible in the case of large lattice mismatch growth i.e hetero-epitaxial growth. The Gaussian distribution theoretically also represents the distribution of the film c-axis with the substrate. 

Figure 4: Omega scanning to judge the tilt of the film c-axis with respect to the substrate 

Please check the measurement configuration in the earlier discussion.

Theory, techniques for Schottky barrier diode evaluation

 Introduction:

In the previous discussions, I have clearly discussed the reason for forming Schottky contact. So, to evaluate the Schottky contact (SC), it is necessary to understand the relevant parameters those are governing the Schottky contact response. The parameters are Schottky barrier height (SBH), (Φ_B), ideality factor (η), effective Richardson’s constant (A**), doping concentration (N_D), and series resistance (R_s). The current (I)- voltage (V) characteristics are mainly for the thermionic emission model for a Schottky barrier diode (SBD). The SBD is very promising for fast switching, high current, low noise, and high-frequency applications. 

Theory of SBD:

The SC of SBD governing equation is shown in equation (1). Where, S Schottky contact area, T operating temperature in Kelvin, V applied voltage, K_B Boltzmann constant,  Richardson’s constant, A* material’s properties.  

The A* is influenced by the optical phonon scattering, quantum-mechanical reflection, electron tunneling over the barrier, inhomogeneous barrier distribution, and, metal contact properties. Therefore, taking these into consideration, A* becomes A**. Then equation (1) can be replaced by (2), where I_s reverse saturation current or leakage current and Φ_B0 Schottky barrier-height at zero bias.

The ideality factor is unity for the TE model. This measure deviation from the TE model of the Schottky contact. The ideality factor considers all the factors that affect the TE model. The factors come from carrier generation, field emission, recombination, thermionic field emission, image-force lowering (Δϕ_B) of the SBH, inhomogeneity of barrier, bias dependence of the SBH, edge leakage etc. For high-quality SC the ideality factor is within 1-1.3.  The image force lowering SBD can be expressed by equation (3), 

where, E_MS maximum electric field strength at the interface, this is more pronounced in reverse bias. The E_MS value is related to the bias voltage and can be expressed by equation (4). However, if the diode series resistance plays a crucial role when the current becomes too high. Then the total voltage drops across the diode and series resistance. The I-V relation is modified by the IRs drop. Then equation (2) becomes like (5) is known as Cheung’s method. 

SBD Evaluation: I-V and C-V methods

When we apply forward bias, and the bias V ≥ 3k_BT/q, then equation (2) can be represented by equation (6). Equation (6) can be written in linear form like (7). The linear fitting intercept gives a reverse saturation current, and the slope represents the ideality factor. Hence using the reverse saturation current relation shown in (2), we can estimate the SBH at zero bias with the known value of the Richardson constant. 

Along with the I-V relation, it is also necessary capacitance-voltage (C-V) relation to extracting the SC parameters. The reverse bias generates a depletion region which means the SBD behaves like a parallel plate capacitor. For an n-type semiconductor under the reverse bias condition, the C-V relation is shown in equation (8). C capacitance per unit area. The slope of 1/C² – V plot represents doping concentration N_D. Also, the intercept, Vi, of the plot related to built-in potential, V_bi. 

Then the zero bias SBH can be calculated by equation (9). where E_C-E_F is related to the effective carrier density (N_c) of the state and follows the relation in (10). 

The Nc strongly depends on the effective mass and operating temperature (equation (11)). 

Hence, from I-V and C-V, we can judge SBD applicability. You may find useful of SBD example in my previous explanation. If you need some help with your understanding, then feel free to comment or reach me.

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What is metal-semiconductor contact? Physics behind it.

 Introduction:

In semiconductor technology, there are two types of contact one is rectifying(Schottky), and another is ohmic contact. So, the type of contact depends on the difference in the work function. The Schottky contact has applications in semiconductor physics and Ohmic contact has an influence on the performance of the device specifically power devices.

Physics behind metal-semiconductor contact

The physics behind the contact nature mainly depends on the doping concentration (Nd) of the semiconductor, temperature (T), and carrier transport mechanism at the metal-semiconductor interface (M-S). There are three carrier transport mechanisms that exist in the M-S interface: Firstly, in the case of low doping concentration, the thermionic emission (TE) model dominates where the temperature plays the main role for carrier transport over barrier height between M-S. Secondly, in the case of intermediate doping concentration thermionic field emission dominates (TFE), and the tunnel barrier also makes an additional contribution. Thirdly, the high doping reduces the tunnel barrier more than the field emission dominates the carrier transport. The following figures explain the phenomenon in detail. In Ohmic contact the thermionic dominant which means non-rectifying M-S contact with negligible resistance which means no disturbance for the current-voltage (I-V) characteristics. 

The contact area mainly determined the total contact resistance, Rc(Ω). It is mainly dependent on the contact area, contact geometry, and obviously the quality of the interface. The quality of ohmic contact is determined by the specific contact resistance ρc (Ω cm² ) and is independent of geometry. ρc depends on Schottky barrier height (SBH), semiconductor doping, quality of the interface, semiconductor surface, metal deposition chamber, etc.

On the other hand, the rectifying M-S contact with asymmetrical and nonlinear (I-V) behaviors is said to be a Schottky contact. This is activated if the metal work function is higher than that of the semiconductor electron affinity. Usually, SBH is varied by surface states, metal-induced gap states, defects, and a thin interfacial layer. The interfacial layer having atomic layer thickness allows tunneling of charge carriers. The potential drops across the interfacial layer result in the lowering of SBH. The surface sometimes acts like an acceptor i.e neutral when empty and negative when occupied and the opposite is true. These acceptors are distributed within a forbidden gap resulting in control of the fermi level. The SBD may also be lowered by the image force called the Schottky effect. The image force is nothing but coulombic force from interface electron to far away positive charge.

To learn more about structural characterization please visit this page.

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You can also find my recent blog post here

What is lattice mismatch in hetero-structural growth?

Introduction

The hetero-structural growth is the growth of A material on B material having different lattice constants. The different lattice constant results in structural deformation which leads to defects in the grown A material. The discrepancy of the A material quality (in terms of crystal perfection) can be easily understood by the lattice mismatch percentage. Lattice mismatch is a very important terminology to understand hetero-structural growth. In hetero-structural growth, the mismatch percentages play an important role to decide the performance of the proposed structure. The researcher can judge their expectation with the reality of the mismatch. This is very popular in device physics to judge defects or defect-free growth (strain film less defect), structural deformation for a new role(tetragonal to ferroelectric orthorhombic phase change leading to new properties of the material in new structure, etc.). 

How to calculate lattice mismatch?

The mismatch is nothing but a mismatched strain in the film against the substrate is used. For example, if we consider Si substrate and HfZrO₂ film of different crystal structures as shown in table I. Then the mismatch can be defined in terms of percentage as follow:

                            Lattice mismatch strain= [a(film)-a(substrate)]/a[substrate]  -----------(1)

Table I: Si and HfZrO2 (HZO) lattice constant

Using equation (1), we can have the lattice mismatch strain in the film. Table II shows the mismatch percentages between cubic Si and HfZrO2 corresponding to their lattice constants executed from the relation. 

Table II: Lattice mismatch percentage between Si and HZO

Using equation (1), we can have the lattice mismatch strain in the film. Table II shows the mismatch percentages between cubic Si and HfZrO2 corresponding to their lattice constants executed from the relation. The sign of the strain can be negative or positioned. The negative sign indicates compressive stress which means the lattice constant of the film is smaller than the substrate. More elaboratively, the compressive stress exists in the film (film lattice smaller than substrate), therefore tensile stress is necessary to accommodate the film lattice with the substrate lattice in the in-plane direction (figure 1). 

Figure 1: Lattice mismatch in-plane lead strain in the film

What is the significance of the mismatch sign?

Fundamentally, the strain is nothing but a ratio of the change in length, radius, area, or volume with respect to its original value and stress in the amount of force applied to or exerted by a body to its surrounding. Please review basic mechanics to understand the detail of the strain and stress phenomenon.

 The opposite is the case for a positive sign. The positive sign of the mismatches indicates tensile stress exists in the film. This tensile stress may lead to the structural change of the film which results in new phenomena in the grown film. Please find the lattice calculation here.

How does the band bending occur in n-type semiconductor at thermal equilibrium?

Band bending (Surface defects)

    We know every surface has defects because of no periodic lattice anymore. It has different bodings than that of bonds in the bulk of the semiconductor. Therefore, the dispersion relation acts differently on the 2D surface than on the bulk side. We can draw the schematic image of the surface with a band diagram similar to bulk in 2D spatial dimension having many states in the band gap. Figure 1 shows the detail of the surface states and band diagram of an n-type semiconductor.  

Figure 1: n-type semiconductor and its surface states

The surface shows many unspecified acceptor states. The Fermi energy of the acceptor and semiconductor will adjust such that the higher Fermi energy will move down-side and defect level Fermi energy will move upwards by delivering electrons to the lower level so that the higher Fermi energy moves to the down-side. Now, if the bulk and surface are in close contact. Three cases will occur in the process.

Case-1: just after the contact, the electrons from the bulk will flow to the empty states of the surface (in this case acceptor level). As a result, the surface will be negatively charged (before there was no charge) as shown in figure 2.

Figure 2: Imagine the electron moving from bulk into the surface (like contacting with the surface)

Case-2: As the surface is negatively charged then the static potential of the surface becomes high and goes (reduced) into bulk as shown in figure 3. Then we get built-in potential (Vb). This shows a path to realize a band bending takes place with the potential energy (-eVb). Further, the negative surface repelled the negative electrons from the bulk into the surface. It is necessary energy to move the electrons to the surface and that is the potential energy.

Figure 3: Potential energy distribution of static charges (negative static charge)

Case-3: The electron transfer continues until the equilibrium state is achieved. This means no difference in the potential energy from the surface side to the bulk where the Fermi energy of the surface equals the Fermi energy of bulk as shown in figure 4.

Figure 4: The surface and bulk in equilibrium.

Space Charge Region

However, this behavior will lead to charge imbalance. The band bending region will not contain any free electrons, but it has static positive charged donor atoms. The fixed or static charges reside in the space charge region (SCR) or static region. The corresponding electric field in the region follows a one-dimensional Poisson relation:

Ex=-dV/dx     (1)

This field starts from the positive charge side and ends at the negative charge side. The positive charge side is the ionized donor atoms (inside bulk), and the negative charge is the excess electron on the surface. The SCR makes a formula for the width d of the region. We assume the positive static charge is distributed homogeneously through the SCR volume. Now the capacitance Cs is approximated by a plate capacitor with half of the distance dcap=d/2. Then the capacitance becomes,

CS= 2εsA/d=Q/V (2)

Where capacitor plates area A, Q charge on the plates, V is the potential difference between the plates. The charge is equal to the donor ionized (ND) in the volume (d.A). Then,

Q=eNDdA  (3)

Now, we can get the width of the space charge region from equation (2) by using equation (3)

 

2εsA/d= eNDdA/V

Or, d=(2εsVbi/eND)1/2   (4)

This is correct with the assumption dcap=d/2. The voltage V is nothing but the built-in (Vbi) potential. This is simply the difference of the Fermi energy as mentioned earlier i.e ΔEF/e. If there is an additional potential Vap from outside, then the total potential is:

V=[(ΔEF/e) +(Vap/e)] (5)

The SCR depth:

d=(1/e)[(2εs (ΔEF+eVap)]/ND) 1/2 (6)

We see that the built-in potential is positive. Therefore, an additional positive Vap will enlarge the width of the space charge region. This means the potential difference is increased between bulk and surface. We can have a similar equation from the versatile Poisson equation. We assume the one-dimensional semiconductor where V(x) is varied. Variation of V(x) is due to the charge density ρ(x) distribution into the semiconductor. The ρ(x) is always the net charge density (including electrons, holes, and ionized charges) of the consideration region. In this case, we only have considered static charges (positive and negative both conditions) on the surface.

-εsd2V(x)/dx2=εsdE(x)/dx=ρ(x)     (7)

The conduction and valence band can be represented by the electrostatic potential V(x) having potential energy -eV(x). Anyway, the band energy in terms of electrons energy,

EC(x)=-eV(x)       (8)

EV(x)=-eV(x)       (9)

In case of homogeneously doped semiconductor

However, in a homogeneously doped semiconductor, there are static charges on the surface. There is no current flow and no neutralization of the static charge. The surface side will create an electric field on the bulk side free carriers near the surface resulting in band bending. Here, we expect two different statuses:

Case-1: The polarity of the surface charge is the same as the free majority carrier inside the semiconductor. Because of the same polarity, the surface charges push the inside charge carriers. The pushing force creates a space charge region. This SCR region is called a depletion region figure 5 (b). The band is bent which means the Ec-EF increases towards the surface. The SCR width depends on the dopant density. It is high with low dopant because the dopant atoms cannot reach the interface. We need many dopants to compensate for the surface charge. Also, the accumulation of minority carriers at the valence band results in inversion layer formation. The inversion phenomenon is shown in figure 5(a).

Case-2: If the surface charge is opposite to the majority carrier, then accumulation takes place near the surface region. Then the free charge carriers can compensate for the surface charges. Therefore, the electric field can’t penetrate to a large extent inside the semiconductor. The behavior is similar to accumulation (figure 5 (d)). The majority of carriers and static surface charge have been designated by yellow and blue spheres respectively. Between accumulation and depletion, there is a flat-band case as shown in figure 5 (c).

Figure 5: Band bending of n-type semiconductor with respect to its surface static charge carrier

Now the discussion about the p-n junction can be visualized in terms of their band bending, potential distribution, and electric field distribution as shown in figure 6.

Figure 6: Band bending of p-n junction views in a gradual process.

The equation (6) only takes the form below. Please take care of the sign of Vap for the calculation theoretical calculation.

d=(1/e)[(2εs (1/ND+1/NA)(ΔEF+eVap)]) 1/2 (10)

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