Judge your MOS CAP C-V measurement conditions.

Introduction 

It is very important to judge mainly volatile or non-volatile metal-oxide-semiconductor field effect transistor (MOSFET) devices for the computer system. The purpose of MOSFET is to switch or retain memory information permanently. The C-V measurement is one of the strong techniques to judge the device’s quality. This is also useful to evaluate new materials as well. We can know useful information about doping density in the semiconductor, carrier lifetimes, oxide thickness, oxide charges, interface trap density, mobile ions, etc. Therefore, understanding the detail of C-V measurement is of prime interest.

Fundamentals of MOS capacitor

For the measurement, it is necessary to the fabricated device in the structure of the Metal/Oxide/Semiconductor/Metal structure. This is like a MOS capacitor as shown in figure 1. In the structure, the semiconductor and bottom metal electrode acts as cathode plate. The top metal on the insulator acts as another electrode (anode). This is complete like a typical capacitor structure. We simply determine the capacitance from C = A (K/d), where A is the area of the capacitor top electrode, K is the dielectric constant of the insulator, and d is the separation distance between the two electrodes. It is clearly seen from the relation that the larger the A and K, and the thinner the d then the higher the capacitance. Anyway, the semiconductor capacitance values range from nano-farads to pico-farads or smaller. C-V measurement concepts: Two ways we can measure the C-V. 1. Quasistatic 2. High frequency. 

Figure 1: Cross-sectional MOS cap structure and measurement configuration

Quasistatic condition 

This is corresponded to close equilibrium. By convention, the quasistatic C-V measurement is made by the sweeping bias voltage applied to the MOS capacitor resulting in the semiconductor surface changes from inversion to depletion and then to accumulation. In this process, the displacement current is measured as a function of time. The displacement current is the transient charging current of the MOS capacitor. Actually, there is no real current flowing through the oxide layer. This quasistatic measurement is useful when the oxide material is not leaky. If it is leaky conduction current will be added to the displacement current and measurements will be inaccurate. For high-quality oxide material, the leaky current is negligible. However, the good point is that modern computer-driven C-V measurement can correct the leakage current. Surely, the integration of charging current results in the measurement of the stored charge in the MOS capacitor. i.e., CV=Q. It is clear that, if the surface of the semiconductor is either in accumulation or inversion denotes the charged mobile carriers are just beneath the oxide. Finally, the maximum capacitance measured is nothing but the capacitance of the oxide layer alone Then, C_max= C_oxA, and A is the area of the gate electrode contact. On the other hand, if the semiconductor is depleted then there is no layer of mobile carriers underneath the oxide/semiconductor interface. The mobile carriers are present underneath the depletion region. Then, in the depletion, the measured C is consisting of the series combination of oxide and capacitance of the depletion region. This series combination means less than C_max. In the measurement, the voltage is swept from inversion to accumulation then capacitance decreases C_max towards minimum. Equation 1 shows the expected C_min relation.

The detailed behaviors are shown in figure 2. Here, x_o and K are the thickness and dielectric constant of the oxide material. X_d and K­_s are the maximum thickness and dielectric constant of the depletion layer (semiconductor part). A note to keep in mind is that there is an electrical charge are still existed within the depletion region due to doping of the semiconductor i.e ionized impurity atoms. The good point is that these ionized charges do not affect or contribute to the displacement current due to its static nature. But at a high temperature, they may move so care about temperature is essential. Usually, room temperature measurement does not affect them. 

Figure 2: Quasistatic C-V response ( p-type semiconductor) 

Earlier we discussed quasistatic measurements where the capacitance is directly measured by the integration of charging current. It requires the application of bias voltages across the capacitor with a superimposed AC signal (Figure 1). Typically, AC frequencies from 10 kHz to 10 MHz are considered for these measurements. The DC bias functions as sweep voltage that drive the capacitor from the accumulation region to the depletion region and goes into inversion as shown in figure 2 or the reverse way. Depending on the polarity of the DC bias and carrier type in the semiconductor the accumulation and depletion occur. The accumulated majority carrier near the surface of the semiconductor cannot pass through the insulator which results in a capacitance maximum in the accumulation region as shown in figure 3. 

Figure 3: High-frequency C-V (p-type semiconductor)

In this case, the capacitance measured under conditions of accumulation and depletion can be expected to be the same as observed in quasistatic measurements. If the frequency of the AC signal is high enough, then the capacitance measured under a condition of inversion is not the same as in the quasistatic case. The reason is the non-equilibrium behavior of the inversion layer. In the physical sense, the inversion layer should be formed from the minority carriers generated in the depletion region and swept to the surface by the electric field. From the bulk minority carriers also can diffuse. In simple understanding, the equilibrium conditions indicate that there is enough time for the inversion layer carrier concentration to respond to any changes in the applied field. In reality, if the semiconductor is good then the carrier generation -recombination processes occur slowly usually for silicon it is in the millisecond orders. So, if the applied AC voltage is in the MHz range, then the inversion layer responses very slowly to flow the signal and is similar to ionized dopant impurity atoms’ behaviors. Apparently, the inversion layer is fixed with the AC component. This behavior is shown in figure 3. The capacitance in the inversion layer is the series combination of oxide and depletion layer capacitance (fully depletion condition).

Deep depletion in C-V Measurements

We can measure capacitance versus voltage either by sweeping the applied voltage from accumulation to inversion (+ to - voltage for n-type; - to + for p-type) or inversion to accumulation. In the case of quasistatic measurements, the direction of the sweep makes essentially no difference in the C-V plot, because the MOS capacitor remains nearly at equilibrium. However, at high frequency, the C-V plot may differ in the inversion region depending on the direction and rate of the voltage sweep. This is due to the kinetics of the minority carrier generation as discussed earlier. If generation and recombination it takes a longer time (excellent substrate), then the inversion layer may not fully form during the fast switching from accumulation to inversion. This may increase the depletion layer than we expect for equilibrium conditions. We call this a deep depletion as mentioned in figure 4. 

Figure 4: Deep depletion sweep from accumulation to inversion

Such deep depletion should be avoided in conventional C-V measurement. Of course, we can take advantage of this situation to determine the time constant of carrier generation-recombination processes i.e minority carriers’ lifetime of the substrate. Anyway, at high frequency, we can find the onset of equilibrium behavior, i.e., MOS capacitance increases in inversion. The minority carrier lifetime can be estimated by determining the dependence of inversion capacitance on sweep rate. The derivative of this function extrapolated back to equilibrium conditions is the minority carrier lifetime. 

Practically high-frequency C-V measurements are nearly always made by sweeping the applied bias voltage from inversion to accumulation to eliminate deep depletion. A point to be noted is that by proper biasing and illumination of the surface the substrate surface is fully inverted for inversion layer formation by illumination. Of course, the sweep should be done without illumination. Of course, the voltage sweep itself should be made without illumination. The ideal MOS capacitance per unit area, C, follows equation 1. Finally, if the substrate doping is constant, an increase in oxide thickness reduces the capacitance of the oxide layer resulting in a reduction of MOS capacitance. Furthermore, the position of the depletion region as a function of bias moves to higher values of voltage magnitude so a higher voltage magnitude must be applied across a thicker oxide to obtain the same electric field magnitude at the oxide/semiconductor interface. Also, if oxide thickness is fixed but substrate doping causes a corresponding change in the depletion layer capacitance. This is well understood that increasing (or decreasing) substrate doping causes the maximum width of the depletion layer to be reduced (or increased). So, at fixed oxide thickness, the Cox remains fixed, but the Cmin varies with substrate doping. Please find information to be extracted from the C-V measurement. You may also have an interest in band bending and p-n junction detail. Please check also them.