What is bandgap? What is doping?

The band gap

    The band gap usually refers to the energy difference between the valence band (EV) and conduction band (EC) energy. In other words, it is the minimum energy that is required for an electron to move from the valence band to the conduction band. In the conduction band, the electron freely moves, resulting in conduction into the semiconductor. Figure 1 shows the basic band diagram of an intrinsic semiconductor. The valence band is lower and the conduction band is higher energy level. The energy gap is Eg. Usually, thermal energy excites the electron from the valence band to the conduction band. If the electron moves from the valence band to the conduction band another electron comes to the empty place from the neighboring atom in the valence band. This continues the electron transfer from the valence band to the conduction band. The sequence represents an electron in the conduction band and a hole in the valence band. The free electron and hole can act as a carrier for conduction. The electron and hole move on opposite sides in crystal material. The fundamental of fermi level EF has broadly discussed elsewhere.

Figure.1. An schematic of the energy band diagram of semiconductor materials

    

Necessity of doping

    However, the intrinsic carrier density (ni) depends on temperature and band gap which influence device performance. The thermal energy (300K) can create a free carrier from the valence band to the conduction band. In the intrinsic semiconductor, the number of electrons and holes are the same in the semiconductor crystal. The thermal energy (300K) corresponds to 0.025 eV. It is difficult to have free electrons and holes for a wide band gap (2-5 eV) semiconductor because the larger thermal is insufficient to exceed the band gap. It is necessary to high temperature to over the band gap.  Anyway, the typical value of intrinsic carrier density in Si at 300 K is around 1E10 [cm-3]. To modulate the carrier concentration, it is necessary to doping into the intrinsic semiconductor.


Doping techniques

    The doping is done by various techniques to increase electrons or holes depending on the purpose. N-type forms when group IV is doped with group-V atoms, and p-type forms when group IV is doped with group III. We can easily choose groups III, IV, or V from the periodic table. The enhancement of the free carrier increases the conductivity of the semiconducting crystal. Figure 2 shows the n-type and p-type semiconductor formation with widely used Si. N-type materials are chosen from group V and added with group IV Si. Group IV Si has four valence electrons and group V has five valence electrons. When the doping process is complete the 2 groups make covalent bonding by sharing their electrons. But group V has one extra electron which is loosely bonded with the group V atom. The thermal energy (300K) is sufficient to free the additional electron into the crystal. This free electron named the materials is n-type. The number of dopants determines the free carrier density for conduction. The n-type doping increases the electron concentration higher in the doped crystal. Now the doped crystal contains the majority of free carrier electrons and minority carrier holes. The opposite is true for the p-type doped cases.


Figure 2: n-type and p-type formation process


Figure 3: After doping the donor and acceptor levels in the band diagram are free to conduct.
 

Figure 3 shows the band diagram of p and n-type semiconductors. When no external bias is applied then the number of carrier concentrations is called equilibrium carrier concentration. According to the mass action law, we can write down the relation of intrinsic carrier concentration with the electron concentration (no) and hole concentration (PO) at equilibrium.

n0p0=ni2  (1)

In n-type, the intrinsic and doped electron makes majority electrons (n0=ND), and minority (p0 as it was before doping). The case is similarly treated for the p-type crystal. In terms of majority and minority carriers, similarly, we can write get for n-type and p-type as follows,

n-type: n0=ND,p0=ni2/ND   (2)

p-type: p0=NA, n0=ni2/NA  (3)

Here, ND is a donor, and NA is an acceptor atoms concentration. The number of minority carriers decreases if the doping is increased. The doping wide modulates carrier concentration which is necessarily interesting for the research community to develop new device technology.

 

P-N junction

    One of the fundamental device structures is a p-n junction. The junction is formed by connecting the p-type semiconductor with the n-type as shown in figure 4. Just after their contact holes from the p-side move to the n-side and electrons from the n-side move to the p-side. This is due to the diffusion process because of the high concentration of their respective side. Static or space charge carriers are generated mainly near the junction which can not move freely. This is due to diffusion. On the p-side negative static and n-side positive static charges are created which are separated by the junction. As a result, an electric field is induced between the positive and negative charges. The static region near the junction is called the depletion region. The electric field (E) sweeps free carrier from the region. That means the region depleted free carriers. The electric field generates a built-in potential at the junction. The detail of the p-n junction under no bias condition is shown in figure 4.

Figure 4: Schematic of p-n junction contact>> neutral region, and dopant, electric field, and potential barrier distribution

The above discussion is a very fundamental explanation to understand the electronics device concept and the associated terms used in device evaluation. Please find a more detailed explanation of the electric field equation, dopant relation with fermi energy, and band diagram of the p-n junction in the subsequent discussion. Also, you can find other valuable technical and scientific discussions here.




Crystal parameters extraction from mix structure of cubic and hexagonal MnAs/InAs/GaAs(111)B heterostructure system.

 X-ray diffraction (XRD)

    Crystal structures are very important for device technology. Specifically, single-crystal or epitaxial grown material systems play a key role to develop device technology on the right track. So, studying crystal structures of novel materials systems is quite important. It is well known that the crystal structure of solid is widely examined by x-ray diffraction (XRD) techniques. The wavelength of the x-ray is around 0.1 to 10 Å. The material structure study is carried out based on the interference principle of x-ray with the materials system. Through the interaction, we can extract crystal parameters. The interference obeying a famous law defined by Bragg is known as Bragg law. We consider a simple crystal structure where crystal parameters (a=b=c) are connected with miller indices (hkl) and interplanar spacing d. It is seen that a monochromatic x-ray beam has a coherent radiation incident on a crystal as shown in the schematic figure 1. 

Diffraction relation examines.

Figure 1: Diffraction relation examines.

The atomic lattice which constitutes diffraction is from parallel planes in symmetric measurement. For the simple cubic system, the d and a, and hkl are related by the following relations,

Similarly for a hexagonal unit cell d is connected as follows. 



Bragg's law derivation

The diffraction peaks are visible from constructive interference of diffracted beams from parallel planes. It is necessary to have an in-phase of diffracted beams after leaving the crystal planes. We labeled beams 1 and 2 in figure 1. Path difference between the two diffracted beams (EF+FG) will be equal to an integral number (n) of the wavelength of the incident x-ray.

EF+FG= nλ (3)

EF=FG then, Sinɵ=EF/d

Therefore, EF=dsinɵ, then equation (3) becomes

nλ=2dsinɵ (4)

It is known as Bragg’s law. This explains the angular relation of diffracted x-ray with their wavelength. For first-order diffraction, (n=1) Bragg’s law becomes,

λ=2dsinɵ (5)

At the diffraction conditions incident angle ω is equal to the diffraction angle ɵ. Through this measurement, we only can have information about interplanar distance and hence lattice constants. The basic XRD measurement setup schematic is shown in figure 2.

Schematic of symmetric XRD measurement
Figure 2: Schematic of symmetric XRD measurement 


Example of lattice parameter extraction

Now, we consider MnAs/InAs/GaAs heterostructure where MnAs is a hexagonal ferromagnetic metal, InAs and GaAs are cubic compound semiconductors. The structure is very important for spintronic device applications. Anyway, we have carried out XRD symmetric diffraction, where incident angle ω and diffraction angle ɵ maintain the same angle during the 2ɵ/ω measurement. Figure 3 shows the measured XRD result. From figure 3, we see diffraction peaks from different planes from respective materials. Hence with angle position information and corresponding Miller indices (hkl), we can extract the lattice parameters using equations (1), (2), and (5). The corresponding lattice parameters of cubic GaAs and InAs are 5.65 and 6.05 Å respectively. The lattice constant of hexagonal MnAs is around 5.71 Å. 

Symmetric ω/2ɵ XRD results of MnAs/InAs/GaAs(111)B
Figure 3: Symmetric ω/2ɵ XRD results of MnAs/InAs/GaAs(111)B

However, for the early rising researcher, this kind of basic study is quite important to develop themselves in science and technology. The above discussion is somehow different from a usual discussion about crystal structure study.  I believe that my little effort will be helpful to understand the mix-crystal structure study. Therefore, I would like to invite people who are really interested in studying crystallography. You may also have an interest in TLM devices, ferromagnetic phase transition-related problem solving, or Schottky diode evaluation for power device applications. These are available in my blog also please check here.   

     

    






How does TLM help to extract contact resistance, specific contact resistivity and re-modeling of TLM for electronic device evaluation?

 

Transmission line method (TLM)

For the semiconductor industry, small and faster device operation is demanded. There are so many factors associated with device performance. The contact resistance in a device is one of them. The typical value of contact resistance of electronic devices is around (10E-8 to 10E-6)  [Ohm-cm2] which is widely reported in many kinds of literature. It usually depends on the contact area. We termed it specific contact resistivity (ρc). This is a figure of merit for ohmic contact and determines interface quality. Mostly, the transmission line method (TLM) is used to extract the contact resistivity. It is made of metal contacts developed in the conducting area. This area has a specific length (Le), and width (W) at the different spacing between them. Figure 1 shows a conceptual model for Metal electrode and semiconductor contact. 

Transmission line method for metal and conducting channel interface

Figure 1: Transmission line method for metal and conducting channel interface

Here, I would like to discuss the basic TLM modeling and subsequently re-modeling of the TLM to fit device structure in a simplified way. So, to measure mainly Ohmic contact in a planner device contact (figure 1), we consider, that the sheet resistance of the channel layer is ((ρs), the resistance per unit length, R=((ρs/W), and potential at metal 0, with potential v(x) and current i(x) at the position x of the channel are,

The Lt is crucial for designing electrode length. We usually call it to transfer length. We can consider total resistance RT between the two metal electrodes (figure 2). The transfer length mainly determines specific contact resistivity. It is defined such that 63% of the current flows into contact. If the lateral contact becomes larger enough than the transfer length, then the contact behaves like semi-infinite contact. It is natural decreasing transfer length contact resistance increases. 


TLM modeling between two contact points

Figure 2: TLM modeling between two contact points

Anyway, if the spacing between two metal electrodes is (L) and total resistance follows a linear relationship, we can extract sheet resistance from the slope and contact resistance from the intercept and hence specific contact resistance by (7) or (8). The total resistance becomes,  it is already seen from the measured TLM where we can extract contact resistance from different L-dependent I-V plots as shown in figure 3, and the important parameters like sheet resistance and contact resistance are extracted from the linear fitting as clearly shown in figure 3. 

From I-V the contact resistance extraction and fitting.

Figure 3: From I-V the contact resistance extraction and fitting.

However, if device processing makes an uneven distribution of channel material thickness between the contacts  (figure 4), re-modeling of the contact has to be carried out. Here, we simply re-model the TML as shown in figure 4.  From the TLM result and the re-model structure, we can know the sheet resistance ρs2 of a channel between the metal electrode and using the ρs2, we find sheet resistance ρs1  of the channel underneath the metal electrode. This can be written in the following form:

Re-modeling of TLM with uneven channel thickness due to device processing

Figure 4: Re-modeling of TLM with uneven channel thickness due to device processing

Where d1 and d2 are channel material thickness underneath the metal electrode and between metal electrodes respectively. I think many researchers face similar problems during developing device structure and unconsciously misinterpret the measured data which results in the failure of their efforts. I hope that my critical thinking about the re-modeling of TLM will help people in device physics to excel in their work properly. Therefore, I would like to welcome people who are really interested in such critical considerations for their work for the development of science and technology. You may also have an interest in ferromagnetic phase transition-related problem solving, or Schottky diode evaluation for power device applications. These are available in my blog also, please check here.  





What is ferromagnetism and phase transition? How to extract second order ferromagnetic phase transition from M-T measurement?

Magnetization

    Ferromagnet shows spontaneous magnetization (M) with or without a magnetic field. The magnetization remains without the field. Usually, the alignment of the magnetic moments of electrons gives spontaneous magnetization. The exchange interaction in quantum mechanics explains the interaction of spin-spin controlled by the Coulomb interaction.  The interaction keeps the Pauli principle stable. If the net magnetization is zero in a system that means exchange interaction is zero. If it is high that means all spins are parallel to each other resulting in non-zero magnetization. However, simply if the temperature (T) is increased then thermal energy will randomize the spins and if the T is very high the randomization will be too much resulting in vanishing magnetization. The vanishing of magnetization means the magnetic system is paramagnetic in nature. The temperature at which the magnetic moment of electron spin orientation vanishes is called critical temperature (Tc) or Curie temperature.


Magnetic phase transition

    We know that the phase transition is usually governed by pressure, chemical composition, temperature, electric or magnetic field, and connected with order. We see two types of phase transition: one is first order and the other is one-second order. The first-order phase transition is discontinuous with entropy and hence with latent heat. For example, if we heat an ice bar at a constant rate, the temperature remains the same until we reach zero degrees Celsius. The heat we put to become zero degrees is the latent heat of transformation. The first order is also known as sudden volume change. For example, ice enlarges relative to water when they transfer to each other i.e. sudden change in volume. On the other hand, a second-order phase transition does not carry any latent heat with it. The entropy is continuous at a critical temperature. Figure 1 (a) and (b) show the graphical representation of the ferromagnetic and paramagnetic nature of the magnetic moment of electron spin. 



Figure 1: (a) ferromagnetic (b) paramagnetic electron spin moment.




Figure 2 shows the first-order and second-order phase transition behaviors concerning temperature.


a) first-order (b) second-order magnetic phase transition
Figure 2. (a) first-order (b) second-order magnetic phase transition 


Magnetic second-order phase transition evaluation

For technical people, it is necessary to extract magnetization transition temperature for application-related or further consideration-related issues. The detailed process is usually in journal papers or proceedings that do not highlight it. Because that is a technical point usually people keep with them. Therefore, understanding how to evaluate magnetic transition, specifically second-order phase transitions is important and necessary to evaluate properly. We consider magnetic thin film having ferromagnetism which is technologically important for spintronic devices like GMR, TMR, spin FET, or novel applications. First, we can measure (SQUID, VSM methods) the saturation magnetization field from the M-H graph (figure 3). Also, from the M-H result, we can easily extract coercive fields to design magnetic devices.

Saturation magnetization determination
Figure 3: Saturation magnetization determination 

Second, use the saturation magnetization field as an applied magnetic field and measure temperature-dependent magnetization, and normalize the magnetization by the volume of the magnetic thin film. Sometimes we need to subtract the background part if there are other film or substrate contributions like diamagnetic involved in the sample. Finally, the first derivation of the M-T curve gives a transition temperature at the minimum of the first derivation. The measurement of M-T and extracted graph are shown in figure 4 (a), and (b) respectively. By this technique, one can successfully extract the important Curie temperature of the magnetic thin film. 

(a) M-T curve and (b) first derivative of M-T minima is the second-order transition point
Figure 4: (a) M-T curve and (b) first derivative of M-T minima is the second-order transition point 

You can also learn about Schottky diode-related related problems.

How to extract background carrier density, built-in potential, barrier height, and ideality factor of a Schottky diode?

Schottky diode
Schottky diode is a metal/semiconductor diode (figure 1). Figure 1 shows a vertical structure of a  Schottky diode and relevant contact. The Schottky contact is the higher potential and Ohmic contact is the lower potential. It works at low forward voltage. Sometimes it is called a hot-carrier diode. This is typically used for fast switching purposes. 

Vertical SBD device structure

Figure 1: Vertical SBD device structure

Considering depletion layer spacing of W and permittivity, the Schottky junction works as a capacitor. The relation among the capacitor parameters is shown in equations (I) and (II) (figure 2) where Vbi is built-in potential, A is the area of the Schottky contact, ND is donor concentration, and V is the applied voltage, q is the electron charge.

Mathematical relation of C and V.
Figure 2: Mathematical relation of C and V.  

By performing C-V measurement (figure 3) and corresponding plotting of 1/(C*C)-V plot, it becomes a linear function of the applied voltage V, equating the slope (equation (II)) with the extracted slope from the 1/C*C-V and using the area A of Schottky contact, charge q, and permittivity constant of the material gives the doping concentration. Also, the extrapolation of the 1/C*C-V to the v axis gives the built-in potential of the diode (see fig. cut the v-axis).
Built-in potential extraction from C-V data.
Figure 3: Built-in potential extraction from C-V data.


Barrier height

It is just a potential difference between the metal Fermi energy and the band edge (after contact with the semiconductor ) to the majority carrier belongs. Figure 4 shows the nature of Schottky contact nature when metal and semiconductor (n-type) contact take place. With forwarding bias, the barrier height reduces, and reverse biased increases the height which is a basic part of p-n junction understanding and they can be found in a solid-state device physics book.
Conceptual Schottky contact.
Figure 4: Conceptual Schottky contact.

However, to extract, barrier height, we require temperature-dependent I-V but alternatively, we can roughly extract the barrier using the following relation as shown in figure 5:

Barrier height extraction method.

Figure 5: Barrier height extraction method.



Ideality factor

The ideality factor defines the properness of the diode. Usually, temperature-dependent I-V measurement is carried out to find out the diode ideality factor because it strongly depends on the temperature and applied voltage. But we can roughly estimate the ideality factor n-from the slope of the small-signal I-V plot. Figure 6 explains the detail of the extraction of n.
Diode ideality factor extraction method.
Figure 6: Diode ideality factor extraction method.

Ideality factor 1.0 means recombination is limited with the help of a minority carrier (band to band or low-level carrier injection takes place). If it is 2.0 then the recombination is controlled by the majority and minority carriers (large injection). If recombination takes place via an isolated point defect, then the ideality factor is 2 or less as predicted by Shockley-Read-Hall recombination assumptions. Further, if it is over 2.0 then a multiple recombination process is involved including majority and minority carriers (Auger or two carrier type controls the recombination process). Usually, the too low field inside the depletion region pushes single-level tunneling by the trap. For two-level recombination, one shallow level is considered and that indicates high defects volume results in a large ideality factor. If we consider that the current is not flowing homogeneously in the diode, then we can consider why the large ideality factor happens even in the low voltage range. We know from some literature the main source of current at high ideality factor due to edge defect when the carrier crosses junction. It is necessary to understand the origin of edge opening during device processing (etching, dicing, or generating amorphous surface during device processing to avoid extending defect density). Also, there are other factors like large series and shunt resistance that causes large ideality factor even at low voltage. You can also learn Magnetic second-order transition.